Fabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowire Fabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowire

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 230
  • Download : 0
Issue Date
2007-05-06
Language
ENG
Citation

211th Electrochemical Society Meeting, pp.0 - 0

URI
http://hdl.handle.net/10203/158274
Appears in Collection
EE-Conference Papers(학술회의논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0