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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Fabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowireFabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowire

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dc.contributor.authorCho, Byung Jin-
dc.contributor.authorYang, WF-
dc.contributor.authorWhang, SJ-
dc.contributor.authorLee, SJ-
dc.contributor.authorZhu, HC-
dc.date.accessioned2013-03-27T02:25:56Z-
dc.date.available2013-03-27T02:25:56Z-
dc.date.created2012-02-06-
dc.date.issued2007-05-06-
dc.identifier.citation211th Electrochemical Society Meeting, v., no., pp.0 - 0-
dc.identifier.urihttp://hdl.handle.net/10203/158274-
dc.languageENG-
dc.titleFabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowire-
dc.title.alternativeFabrication and characterization of 65nm gate length p-MOSFET integrated with bottom up grown Si nanowire-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage0-
dc.citation.endingpage0-
dc.citation.publicationname211th Electrochemical Society Meeting-
dc.identifier.conferencecountryUnited States-
dc.identifier.conferencecountryUnited States-
dc.contributor.localauthorCho, Byung Jin-
dc.contributor.nonIdAuthorYang, WF-
dc.contributor.nonIdAuthorWhang, SJ-
dc.contributor.nonIdAuthorLee, SJ-
dc.contributor.nonIdAuthorZhu, HC-
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EE-Conference Papers(학술회의논문)
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