Development of three-dimensional memory die stack packages using polymer insulated sidewall technique

A newly designed three dimensional (3-D) memory die stack package has been established, and the prototype of the 3-D package using mechanical dies has been successfully demonstrated. Fabrication processes of the 3-D package consist of 1) wafer cutting into die segments, 2) die passivation including sidewall insulation, 3) via opening on the original I/O pads, 4) I/O redistribution from center pads to sidewall, 5) bare die stacking using polymer adhesive, 6) sidewall interconnection, and 7) solder balls attachment. There are several significant improvements in this new 3-D package design compared with the current 3-D package concept. The unique feature of this newly developed package is the sidewall insulation of dies prior to the I/O redistribution of dies, which produces 1) better chip-to-wafer yields and 2) significant process simplification during subsequent fabrication steps. According to this design, 100% of die yields on a conventional wafer design can be obtained without any neighboring die losses which usually occur during the I/O redistribution processes of conventional 3-D package design. Furthermore, the new 3-D package design can simplify the following processes such as I/O redistribution, sidewall insulation, sidewall interconnection, and package formation. It is proven that the mechanical integrity of the prototype 3-D stacked package meets requirements of the JEDEC Level III and 85 degrees C/85% test.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2000-05
Language
ENG
Citation

IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.23, no.2, pp.252 - 256

ISSN
1521-3323
URI
http://hdl.handle.net/10203/1224
Appears in Collection
MS-Journal Papers(저널논문)
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