Temporal partitioning to amortize reconfiguration overhead for dynamically reconfigurable architectures

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In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limitation. By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. And then, we will present benchmark results to demonstrate the effectiveness of our methodology.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2007-12
Language
English
Article Type
Article
Keywords

COMPILER; SYSTEMS

Citation

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E90D, pp.1977 - 1985

ISSN
0916-8532
DOI
10.1093/ietisy/e90-d.12.1977
URI
http://hdl.handle.net/10203/12023
Appears in Collection
EE-Journal Papers(저널논문)
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