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PrePack: Predictive packetizing scheme for reducing channel traffic in transaction-level hardware/software co-emulation Lee, Jae-Gon; Kyung, Chong-Min, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.25, no.10, pp.1935 - 1949, 2006-10 |
Simulation acceleration of transaction-level SoC design with RTL sub-blocks = 레지스터 전송 수준 하위 블록을 포함한 트랜잭션 수준 SoC 디자인의 시뮬레이션 가속link Lee, Jae-Gon; 이재곤; et al, 한국과학기술원, 2006 |
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