This paper presents a scheme called PrePack for suppressing the channel traffic between simulator and accelerator in the accelerator-based hardware/software co-emulation where the accelerator models some register transfer level (RTL) subblocks while the simulator runs transaction-level modeling (TLM) of the remaining part of the design under verification (DUV). With the conventional simulation accelerator, a cycle 'consisting of a pair of evaluations of simulator and accelerator occurs at every valid simulation time, which results in poor simulation performance due to the overhead of simulator-accelerator channel access, often accounting for more than 99% of total channel traffic time (total channel traffic time consists of channel-access time for arbitration/protocol exchange and pure data/signal transmission time). The overhead due to channel access can be reduced by merging as many channel transactions on the channel as possible into a single burst traffic, which is achieved in this paper by "prediction and rollback." In the proposed "prediction and rollback" scheme, one of the two verification domains, i.e., software simulation and hardware acceleration, leads the other, while the leading domain predicts the states of the lagging domain. Therefore, the evaluation of simulator and accelerator no longer need to alternate at every simulation cycle. Under an ideal condition with 100% prediction accuracy, PrePack has shown a 15 x speedup compared to the conventional scheme. When applied to advanced encryption standard (AES) and joint photographic experts group (JPEG) example systems, PrePack showed performance gains of 8.7 and 2.9, respectively.