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A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration Chang, Dong-Jin; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.3, pp.281 - 285, 2018-03 |
Background Calibration을 이용한 12-bit 500MS/s Binary-Weighted 전류 구동 DAC = A 12-bit 500MS/s binary-weighted current steering DAC with background calibrationlink 최영재; Choi, Young-Jae; et al, 한국과학기술원, 2014 |
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