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Showing results 2981 to 3000 of 275953
| A 1.5V, 140uA CMOS ultra-low power common-gate LNA Jeong C.J.; Qu W.; Sun Y.; Yoon D.Y.; Han S.K.; Lee, Sang-Gug, 2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011, IEEE, 2011-06-05 |
| A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme Kim, Y.; Sung, K.-H.; Kim, Lee-Sup, 2002 IEEE International Symposium on Circuits and Systems, pp.I-461 - I-464, IEEE, 2002-05-26 |
| A 1.7-GHz GaN MMIC Doherty Power Amplifier using an Adaptive Bias Circuit with a Quadrature Coupler Lee, Seungkyeong; Lee, Sangmin; Hong, Songcheol, 2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2017), IEEE, 2017-09-01 |
| A 1.8 to 2.4-GHz 20mW digital-intensive RF sampling receiver with a noise-canceling bandpass low-noise amplifier in 90nm CMOS Lee, J.; Kim, J.; Cho, SeongHwan, 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010, pp.293 - 296, IEEE, 2010-05-23 |
| A 1.8 V 900 mu W 4.5 GHz VCO and Prescaler in 0.18 mu m CMOS Using Charge-Recycling Technique Park, Dong-Min; Cho, Seong-Hwan, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.19, pp.104 - 106, 2009-02 |
| A 1.8-GHz CMOS power amplifier using a dual-primary transformer with improved efficiency in the low power region Park, Changkun; Han, Jeonghu; Kim, Haksun; Hong, Songcheol, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.56, no.4, pp.782 - 792, 2008-04 |
| A 1.8-GHz CMOS Power Amplifier Using Stacked nMOS and pMOS Structures for High-Voltage Operation Son, Ki-Yong; Park, Chang-Kun; Hong, Song-Cheol, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.57, no.11, pp.2652 - 2660, 2009-11 |
| A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching Park, CH; Kim, O; Kim, Beom-Sup, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.5, pp.777 - 783, 2001-05 |
| A 1.8-GHz Self-calibrated Phase-locked Loop with Precise I/Q Matching Beom-Sup Kim, AP-ASIC 2000 Proceedings of the Second IEEE Asia Pacific Conference on, pp.81 - 84, IEEE, 2000-08 |
| A 1.83 GHz 28.5 dBm CMOS Power Up-Mixer Paek, Ji-Seon; Hong, Song-Cheol, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.19, no.6, pp.389 - 391, 2009-06 |
| A 1.8dB NF 112mW single-chip diversity tuner for 2.6GHz S-DMB applications Hwang, M.-W.; Beck, S.; Min, S.; Lee, S.; Yoo, S.; Lim, K.; Jung, H.; et al, 2006 IEEE International Solid-State Circuits Conference, ISSCC, IEEE, 2006-02-06 |
| A 1.9 GHz High Dynamic Range CMOS Power Amplifier 홍성철; 박창근; 김윤석; 한정후; 이동호; 백동현, 실리콘RF집적회로 기술워크샵, pp.438 -, 2005 |
| A 1.9-GHz cmos power amplifier using an interdigitated transmission line transformer Park, Changkun; Baek, Sang-Hyun; Ku, Bon-Hyun; Hong, Songcheol, MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, v.49, no.12, pp.3162 - 3166, 2007-12 |
| A 1.9-GHz CMOS power amplifier using three-port asymmetric transmission line transformer for a polar transmitter Park, Changkun; Kim, Younsuk; Kim, Haksun; Hong, Songcheol, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.55, no.2, pp.230 - 238, 2007-02 |
| A 1.9-GHz triple-mode class-E power amplifier for a polar transmitter Park, C; Kim, Y; Kim, H; Hong, Songcheol, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.17, no.2, pp.148 - 150, 2007-02 |
| A 1.93 TOPS/W Scalable Deep Learning/Inference Processor with Tetra-parallel MIMD Architecture for Big Data Applications Yoo, Hoi-Jun; Park, Seongwook; Bong, Kyeongryeol; Shin, Dongjoo; Lee, Jinmook; Choi, Sungpill, IEEE International Solid- State Circuits Conference, pp.80 - 81, IEEE, 2015-02-23 |
| A 1.9nJ/pixel Embedded Deep Neural Network Processor for High Speed Visual Attention in a Mobile Vision Recognition SoC Yoo, Hoi Jun; Hong, In Joon; Park, Seong Wook; Park, Jun Young, IEEE Asian Solid-State Circuits Conference(A-SSCC), pp.185 - 188, IEEE, 2015-11-10 |
| A 10 bit gray scale digital-to-analog converter with an interpolating buffer amplifier for AMLCD column drivers Lee, H.-M.; Son, Y.-S.; Jeon, Y.-J.; Jeon, J.-Y.; Lee, G.-H.; Jung, S.-C.; Cho, Gyu-Hyeong, 2007 SID International Symposium, pp.346 - 349, Society for Information Display, 2007-05-23 |
| A 10 bit piecewise linear cascade interpolation dac with loop gain ratio control Lee, Sungwoo; Kim, Kiduk; Park, Kyusung; Park, Changbyung; Lee, Byunghun; Jeon, Jinyong; Jung, Seungchul; et al, 2010 IEEE Custom Integrated Circuits Conference -CICC 2010, IEEE, 2010-09 |
| A 10 bit piecewise linear cascade interpolation DAC with loop gain ratio control Lee, S.; Kim, K.; Park, K.; Park, C.; Lee, B.; Jeon, J.; Huh, J.; et al, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, CICC 2010, 2010-09-19 |
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