DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, Jae-Sung | ko |
dc.contributor.author | Yu, Chang-Hyo | ko |
dc.contributor.author | Kim, Dong-Hyun | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2013-03-11T17:55:31Z | - |
dc.date.available | 2013-03-11T17:55:31Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2011-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.4, pp.525 - 537 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/99797 | - |
dc.description.abstract | This paper presents a fully programmable 3-D graphics processor using unified shaders for mobile environment. In the system level, we adopted dual-core, dual-issue VLIW, and multithreading methods to utilize instruction, data, and task level parallelism in the graphics applications. In the shader core level, a novel IEEE-754 compliant 4-D vector inner product arithmetic unit and a configurable texture cache are proposed. Using these methods, the proposed processor achieves 143 Mvertices/s and 2.3 Gtexels/s consuming the power of 367 mW. The evaluation shows significant performance and power-delay product benefits. For real graphics applications, test results indicate 2.07 times improvement in performance and 34% reduction in power-delay product compared to previous mobile 3-D graphics processors. The proposed 3-D graphics processor is implemented in 4.5 x 4.5 mm using 0.18-mu m CMOS technology. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | MOBILE APPLICATIONS | - |
dc.subject | VERTEX PROCESSOR | - |
dc.subject | ARCHITECTURE | - |
dc.subject | SYSTEMS | - |
dc.subject | SOC | - |
dc.title | A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache | - |
dc.type | Article | - |
dc.identifier.wosid | 000288681400001 | - |
dc.identifier.scopusid | 2-s2.0-79953081001 | - |
dc.type.rims | ART | - |
dc.citation.volume | 19 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 525 | - |
dc.citation.endingpage | 537 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Yu, Chang-Hyo | - |
dc.contributor.nonIdAuthor | Kim, Dong-Hyun | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | 3-D graphics | - |
dc.subject.keywordAuthor | configurable cache | - |
dc.subject.keywordAuthor | unified shader | - |
dc.subject.keywordAuthor | vector inner product | - |
dc.subject.keywordAuthor | VLIW | - |
dc.subject.keywordPlus | MOBILE APPLICATIONS | - |
dc.subject.keywordPlus | VERTEX PROCESSOR | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordPlus | SOC | - |
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