A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency

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This paper presents the algorithm and implementation of a new high-performance functional unit for floating-point four-dimensional vector inner product (4D dot product; DP4), which is most frequently performed in 3D graphics application. The proposed IEEE-compliant DP4 unit computes Z = AB + CD + EF + GH in one path and keeps the intermediate rounding by IEEE-754 rounding to nearest even. The intermediate rounding is merged with shift alignment, and intermediate carry-propagated addition and normalization are omitted to reduce latency in the proposed architecture. The proposed DP4 unit is implemented with 0.18-mu m CMOS technology and has 12.8-ns critical path delay, which is reduced by 45.5 percent compared to a previous DP4 implementation using discrete multipliers and adders. The proposed DP4 unit also reduces the cycle time of 3D graphics applications by 12.4 percent on the average compared to the usual 3D graphics FPU based on four-way multiply-add-fused units.
Publisher
IEEE COMPUTER SOC
Issue Date
2009-07
Language
English
Article Type
Article
Keywords

DESIGN

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.58, pp.890 - 901

ISSN
0018-9340
DOI
10.1109/TC.2008.210
URI
http://hdl.handle.net/10203/99762
Appears in Collection
EE-Journal Papers(저널논문)
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