DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Jin-Ook | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.date.accessioned | 2013-03-11T17:22:12Z | - |
dc.date.available | 2013-03-11T17:22:12Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2009-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.56, no.12, pp.916 - 920 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/99718 | - |
dc.description.abstract | A new discrete wavelet transform (DWT) architecture is proposed to realize a memory-efficient 2-D DWT processor. The proposed DWT processor conforms to dual-line scanning to remove the transpose buffer. In the previous single-line DWT architectures, the transpose buffer size is proportional to the row size of the image. The conventional dual-line DWT architecture is constructed by using the convolution-based filter structure and replicates registers to alternatively deal with two lines, resulting in a long delay, as well as a number of operators and registers. The proposed architecture is based on the lifting-based DWT to embed the additional registers in the middle of the DWT operation. In addition, the computation topology is optimized for the proposed dual-line DWT architecture to achieve almost the same hardware cost and critical path as the single-line DWT architecture. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | EFFICIENT ARCHITECTURES | - |
dc.subject | MEMORY | - |
dc.title | Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines | - |
dc.type | Article | - |
dc.identifier.wosid | 000272845600008 | - |
dc.identifier.scopusid | 2-s2.0-73149120714 | - |
dc.type.rims | ART | - |
dc.citation.volume | 56 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 916 | - |
dc.citation.endingpage | 920 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2009.2035257 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Digital cinema initiative (DCI) | - |
dc.subject.keywordAuthor | discrete wavelet transform (DWT) | - |
dc.subject.keywordAuthor | pipeline processing | - |
dc.subject.keywordPlus | EFFICIENT ARCHITECTURES | - |
dc.subject.keywordPlus | MEMORY | - |
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