DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, HO | ko |
dc.contributor.author | Lee, BH | ko |
dc.contributor.author | Kim, JT | ko |
dc.contributor.author | Choi, JY | ko |
dc.contributor.author | Choi, KM | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.date.accessioned | 2013-03-11T12:37:40Z | - |
dc.date.available | 2013-03-11T12:37:40Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-03 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.18, no.3, pp.505 - 509 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/99334 | - |
dc.description.abstract | Power-gating has been widely used to reduce subthreshold leakage current. However, the extent of leakage saving through power-gating diminishes with technology scaling due to gate leakage of data-retention circuit elements. Furthermore, power-gating involves substantial increase of area and wirelength. A circuit technique called supply switching with ground collapse (SSGC) has recently been proposed to overcome the limitation of power-gating. The circuit technique is successfully applied to the register file of ARM9 microprocessor in a 1.2 V, 65-nm CMOS process, and the measured result is reported for the first time. The leakage current is reduced by a factor of 960 on average of 83 dies at 25 C, and by a factor of 150 at 85 C. Compared to a register file implemented in conventional power-gating, leakage current is cut by a factor of 2.2, demonstrating that SSGC can be a substitute for power-gating in nanometer CMOS. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CIRCUITS | - |
dc.title | Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000274995400016 | - |
dc.identifier.scopusid | 2-s2.0-77649189595 | - |
dc.type.rims | ART | - |
dc.citation.volume | 18 | - |
dc.citation.issue | 3 | - |
dc.citation.beginningpage | 505 | - |
dc.citation.endingpage | 509 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2009.2012429 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.contributor.nonIdAuthor | Kim, HO | - |
dc.contributor.nonIdAuthor | Lee, BH | - |
dc.contributor.nonIdAuthor | Kim, JT | - |
dc.contributor.nonIdAuthor | Choi, JY | - |
dc.contributor.nonIdAuthor | Choi, KM | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Leakage | - |
dc.subject.keywordAuthor | low-power | - |
dc.subject.keywordAuthor | power gating | - |
dc.subject.keywordAuthor | register file | - |
dc.subject.keywordAuthor | standard cell | - |
dc.subject.keywordPlus | CIRCUITS | - |
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