A novel output driving scheme is proposed to reduce the active matrix liquid crystal display (AMLCD) driver size, especially, the digital-to-analog converter (DAC) size. In this scheme, two channels share one DAC, and the effective area of the DAC in a column driver is reduced by half. Both two column drivers write their data simultaneously; the writing time can be almost the same as one horizontal time, not half. The offset voltage of the operational amplifier is averaged in 2 frames. A simulation is performed with Cadence SPECTRE (TM) under a 0.35-mu m CMOS process. The simulated integral nonlinearity (INL) result is less than +/- 011 LSB, and differential nonlinearity (DNL) is less than +/- 0.014 LSB with 10-bit color depth.