DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Yeong-Dae | ko |
dc.contributor.author | Joo, BJ | ko |
dc.contributor.author | Choi, SY | ko |
dc.date.accessioned | 2013-03-11T08:13:44Z | - |
dc.date.available | 2013-03-11T08:13:44Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.23, pp.246 - 254 | - |
dc.identifier.issn | 0894-6507 | - |
dc.identifier.uri | http://hdl.handle.net/10203/98747 | - |
dc.description.abstract | This paper focuses on the problem of scheduling wafer lots on diffusion workstations in a semiconductor wafer fabrication facility. In a diffusion workstation, there are multiple identical machines, and each of them can process a (limited) number of wafer lots at a time. Wafer lots can be classified into several product families, and wafer lots that belong to the same product family can be processed together as a batch. Processing times and setup times for wafer lots of the same product family are the same, but ready times of the wafer lots (at the diffusion workstation) may be different. We present several heuristic algorithms for the problem with the objective of minimizing total tardiness. For evaluation of performance of the suggested algorithms, a series of computational experiments is performed on randomly generated test problems. Results show that the suggested algorithms perform better than algorithms currently used in practice. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | INCOMPATIBLE JOB-FAMILIES | - |
dc.subject | BATCH PROCESSING MACHINE | - |
dc.subject | TOTAL WEIGHTED TARDINESS | - |
dc.subject | MINIMIZE TOTAL TARDINESS | - |
dc.subject | UNEQUAL READY TIMES | - |
dc.subject | SETUP TIMES | - |
dc.subject | SINGLE-MACHINE | - |
dc.subject | GENETIC ALGORITHM | - |
dc.subject | PARALLEL MACHINES | - |
dc.subject | RELEASE DATES | - |
dc.title | Scheduling Wafer Lots on Diffusion Machines in a Semiconductor Wafer Fabrication Facility | - |
dc.type | Article | - |
dc.identifier.wosid | 000277342400012 | - |
dc.identifier.scopusid | 2-s2.0-77951999622 | - |
dc.type.rims | ART | - |
dc.citation.volume | 23 | - |
dc.citation.beginningpage | 246 | - |
dc.citation.endingpage | 254 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | - |
dc.identifier.doi | 10.1109/TSM.2010.2045666 | - |
dc.contributor.localauthor | Kim, Yeong-Dae | - |
dc.contributor.nonIdAuthor | Joo, BJ | - |
dc.contributor.nonIdAuthor | Choi, SY | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Diffusion | - |
dc.subject.keywordAuthor | heuristics | - |
dc.subject.keywordAuthor | scheduling | - |
dc.subject.keywordAuthor | tardiness | - |
dc.subject.keywordAuthor | wafer fabrication | - |
dc.subject.keywordPlus | INCOMPATIBLE JOB-FAMILIES | - |
dc.subject.keywordPlus | BATCH PROCESSING MACHINE | - |
dc.subject.keywordPlus | TOTAL WEIGHTED TARDINESS | - |
dc.subject.keywordPlus | MINIMIZE TOTAL TARDINESS | - |
dc.subject.keywordPlus | UNEQUAL READY TIMES | - |
dc.subject.keywordPlus | SETUP TIMES | - |
dc.subject.keywordPlus | SINGLE-MACHINE | - |
dc.subject.keywordPlus | GENETIC ALGORITHM | - |
dc.subject.keywordPlus | PARALLEL MACHINES | - |
dc.subject.keywordPlus | RELEASE DATES | - |
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