DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Joo-Young | ko |
dc.contributor.author | Oh, Se-Jong | ko |
dc.contributor.author | Lee, Seung-Jin | ko |
dc.contributor.author | Kim, Min-Su | ko |
dc.contributor.author | Oh, Jin-Wook | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2013-03-11T06:54:13Z | - |
dc.date.available | 2013-03-11T06:54:13Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-06 | - |
dc.identifier.citation | SIGNAL PROCESSING-IMAGE COMMUNICATION, v.25, no.5, pp.363 - 376 | - |
dc.identifier.issn | 0923-5965 | - |
dc.identifier.uri | http://hdl.handle.net/10203/98586 | - |
dc.description.abstract | In this paper, an attention controlled multi-core architecture is proposed for energy efficient object recognition. The proposed architecture employs two IP layers having different roles for energy efficient recognition processing: the attention/control IPs compute regions-of-interest (ROIs) of the entire image and control the multiple processing cores to perform local object recognition processing on selected area. To this end, a task manager is proposed to perform dynamic scheduling of various ROI tasks from the attention IP to multiple cores in a unit of small-sized grid-tile. Thanks to a number of grid-tile threads generated by the task manager, the utilization of the multiple cores amounts to 92% on average. As a result, the proposed architecture achieves 2.1 x energy reduction in multi-core recognition system by indicating processing cores to focus on critical area of the image with a 0.87 mJ attention processing. Finally, the proposed architecture is implemented in 0.13 mu m CMOS technology and the fabricated chip verifies 3.2 x lower energy dissipation per frame than the state-of-the-art object recognition processor. (C) 2010 Elsevier B.V. All rights reserved. | - |
dc.language | English | - |
dc.publisher | ELSEVIER SCIENCE BV | - |
dc.title | An attention controlled multi-core architecture for energy efficient object recognition | - |
dc.type | Article | - |
dc.identifier.wosid | 000279627500007 | - |
dc.identifier.scopusid | 2-s2.0-78650524255 | - |
dc.type.rims | ART | - |
dc.citation.volume | 25 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 363 | - |
dc.citation.endingpage | 376 | - |
dc.citation.publicationname | SIGNAL PROCESSING-IMAGE COMMUNICATION | - |
dc.identifier.doi | 10.1016/j.image.2010.03.003 | - |
dc.contributor.localauthor | Kim, Joo-Young | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Oh, Se-Jong | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Attention controlled | - |
dc.subject.keywordAuthor | Multi-core architecture | - |
dc.subject.keywordAuthor | Object recognition | - |
dc.subject.keywordAuthor | Visual attention | - |
dc.subject.keywordAuthor | Energy efficient | - |
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