Memory bandwidth saving by hardware tessellation with vertex shader

Abstract

Hardware architecture of a tessellator based on a vertex shader is proposed to save memory bandwidth for a mobile 3D graphics engine. According to the appropriate separation of the tessellation process, the powerful performance of a vertex shader, 120 Mvertices/s, is utilised for floating point computations. The remaining part of the process is handled by a dedicated control unit, implementation of which requires 6.2% additional logic gates. The proposed tessellator reduces the bandwidth consumed to transfer 3D geometry data up to 1/250.