Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package

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A new hybrid modeling method is proposed for the chip-package comodeling and coanalysis. This method is designed to investigate the simultaneous switching noise (SSN) coupling paths and effects on the dc output voltage offset of the operational amplifier (OpAmp). It combines an analytical model of the circuit with a power distributed network (PDN) and interconnection models at the chip and package substrate. In order to validate the proposed model, CMOS OpAmp was fabricated using TSMC 0.25 mu m. Then the dc output offset voltage of the OpAmp was measured by sweeping the SSN frequency from 10 MHz up to 3 GHz. It was successfully demonstrated that the experimental results are consistent with the predictions generated using the proposed model. We also confirmed that the dc offset voltage is strongly dependent on the SSN frequency and the PDN impedance profile of the chip-package hierarchical PDN. It shows the necessity for the chip-package comodeling and simulation of the system-in-package designs.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2009-08
Language
English
Article Type
Article
Keywords

TRANSMISSION MATRIX-METHOD; SIGNAL

Citation

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.51, no.3, pp.763 - 773

ISSN
0018-9375
URI
http://hdl.handle.net/10203/94647
Appears in Collection
EE-Journal Papers(저널논문)
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