A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

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dc.contributor.authorBae, Dong-Ilko
dc.contributor.authorRyu, Seong-Wanko
dc.contributor.authorGu, Bonsangko
dc.contributor.authorChoi, Yang-Kyuko
dc.date.accessioned2013-03-08T15:46:09Z-
dc.date.available2013-03-08T15:46:09Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2010-02-
dc.identifier.citationMICROELECTRONIC ENGINEERING, v.87, no.2, pp.135 - 138-
dc.identifier.issn0167-9317-
dc.identifier.urihttp://hdl.handle.net/10203/93458-
dc.description.abstractNew investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM. multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (IT) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of IT DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices. (C) 2009 Elsevier B.V. All rights reserved.-
dc.languageEnglish-
dc.publisherELSEVIER SCIENCE BV-
dc.titleA new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM-
dc.typeArticle-
dc.identifier.wosid000273292700009-
dc.identifier.scopusid2-s2.0-70450255192-
dc.type.rimsART-
dc.citation.volume87-
dc.citation.issue2-
dc.citation.beginningpage135-
dc.citation.endingpage138-
dc.citation.publicationnameMICROELECTRONIC ENGINEERING-
dc.identifier.doi10.1016/j.mee.2009.06.027-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorUnified RAM (URAM)-
dc.subject.keywordAuthorMulti-dual cell (MDC)-
dc.subject.keywordAuthorSoft programming-
dc.subject.keywordAuthorBackground programming-
dc.subject.keywordAuthorOne-transistor (1T) capacitorless DRAM-
dc.subject.keywordAuthorNon-volatile memory (NVM)-
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