DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Seung-Jin | ko |
dc.contributor.author | Kim, Min-Su | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.contributor.author | Kim, Kwan-Ho | ko |
dc.contributor.author | Kim, Joo-Young | ko |
dc.date.accessioned | 2013-03-08T15:00:45Z | - |
dc.date.available | 2013-03-08T15:00:45Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2009-01 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, no.1, pp.136 - 147 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/93340 | - |
dc.description.abstract | A network-on-chip (NoC) based parallel processor is presented for bio-inspired real-time object recognition with visual attention algorithm. It contains an ARM10-compatible 32-bit main processor, 8 single-instruction multiple-data (SIMD) clusters with 8 processing elements in each cluster, a cellular neural network based visual attention engine (VAE), a matching accelerator, and a DMA-like external interface. The VAE with 2-D shift register array finds salient objects on the entire image rapidly. Then, the parallel processor performs further detailed image processing within only the pre-selected attention regions. The low-latency NoC employs dual channel, adaptive switching and packet-based power man- agement, providing 76.8 GB/s aggregated bandwidth. The 36 mm(2) chip contains 1.9 M gates and 226 kB SRAM in a 0.13 mu m 8-metal CMOS technology. The fabricated chip achieves a peak performance of 125 GOPS and 22 frames/sec object recognition while dissipating 583 mW at 1.2 V. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine | - |
dc.type | Article | - |
dc.identifier.wosid | 000262328200014 | - |
dc.identifier.scopusid | 2-s2.0-58149234155 | - |
dc.type.rims | ART | - |
dc.citation.volume | 44 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 136 | - |
dc.citation.endingpage | 147 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2008.2007157 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.localauthor | Kim, Joo-Young | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | Matching accelerator | - |
dc.subject.keywordAuthor | network-on-chip (NoC) | - |
dc.subject.keywordAuthor | object recognition | - |
dc.subject.keywordAuthor | parallel processor | - |
dc.subject.keywordAuthor | processing element clusters | - |
dc.subject.keywordAuthor | visual attention engine | - |
dc.subject.keywordPlus | CELLULAR NEURAL-NETWORKS | - |
dc.subject.keywordPlus | RECOGNITION PROCESSOR | - |
dc.subject.keywordPlus | IMPLEMENTATION | - |
dc.subject.keywordPlus | DESIGN | - |
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