Asynchronous layered interface of multimedia SoCs for multiple outstanding transactions

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 384
  • Download : 0
DC FieldValueLanguage
dc.contributor.authorJung, Eun-Guko
dc.contributor.authorHar, Dongsooko
dc.contributor.authorLee, Jeong-Gunko
dc.contributor.authorJhang, Kyoung-Sonko
dc.contributor.authorLee, Jeong-Ako
dc.date.accessioned2013-03-08T14:28:44Z-
dc.date.available2013-03-08T14:28:44Z-
dc.date.created2013-01-10-
dc.date.created2013-01-10-
dc.date.created2013-01-10-
dc.date.created2013-01-10-
dc.date.issued2007-03-
dc.identifier.citationJOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, v.46, no.2-3, pp.133 - 151-
dc.identifier.issn0922-5773-
dc.identifier.urihttp://hdl.handle.net/10203/93259-
dc.description.abstractIn this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.-
dc.languageEnglish-
dc.publisherSPRINGER,-
dc.titleAsynchronous layered interface of multimedia SoCs for multiple outstanding transactions-
dc.typeArticle-
dc.identifier.wosid000245923000006-
dc.identifier.scopusid2-s2.0-34147178440-
dc.type.rimsART-
dc.citation.volume46-
dc.citation.issue2-3-
dc.citation.beginningpage133-
dc.citation.endingpage151-
dc.citation.publicationnameJOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY-
dc.identifier.doi10.1007/s11265-006-0019-4-
dc.contributor.localauthorHar, Dongsoo-
dc.contributor.nonIdAuthorJung, Eun-Gu-
dc.contributor.nonIdAuthorLee, Jeong-Gun-
dc.contributor.nonIdAuthorJhang, Kyoung-Son-
dc.contributor.nonIdAuthorLee, Jeong-A-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle; Proceedings Paper-
dc.subject.keywordAuthormultiple outstanding transactions-
dc.subject.keywordAuthorin-order/out-of-order transaction completion-
dc.subject.keywordAuthorasynchronous on-chip bus-
dc.subject.keywordAuthorGALS-
dc.subject.keywordPlusDESIGN-
Appears in Collection
GT-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0