Novel structures for a 2-bit per cell of nonvolatile memory using an asymmetric double gate

Abstract

A 2-bit operational metal/silicon-oxide-nitride-oxidesilicon (MONOS/SONOS) nonvolatile memory using an asymmetric double-gate (ASDG) MOSFET was studied to double flash memory density. The 2-bit programming and erasing was performed by Fowler-Nordheim (IN) tunneling in a NAND array architecture using individually controlled gates. A threshold voltage shift of programmed states for the 2-bit operation was investigated with the aid of a SILVACO (R) simulator in both sides of the gate by changing gate workfunctions and tunneling oxide thicknesses. In this paper, the scalability of the device down to 30 nm was demonstrated by numerical simulation. Additionally, guidelines of the 2-bit ASDG nonvolatile memory (NVM) structure and operational conditions were proposed for "program," "read," and "erase".