SAT-based unbounded symbolic model checking

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dc.contributor.authorKang, HJko
dc.contributor.authorPark, In-Cheolko
dc.date.accessioned2007-07-26T10:00:24Z-
dc.date.available2007-07-26T10:00:24Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2005-02-
dc.identifier.citationIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.24, no.2, pp.129 - 140-
dc.identifier.issn0278-0070-
dc.identifier.urihttp://hdl.handle.net/10203/890-
dc.description.abstractThis paper describes a Boolean satisfiability checking (SAT)-based unbounded symbolic model-checking algorithm. The conjunctive normal form is used to represent sets of states and transition relation. A logical operation on state sets is implemented as an operation on conjunctive normal form formulas. A satisfy-all procedure is proposed to compute the existential quantification required in obtaining the preimage and fix point. The proposed satisfy-all procedure is implemented by modifying a SAT procedure to generate all the satisfying assignments of the input formula, which is based on new efficient techniques such as line justification to make an assignment covering more search space, excluding clause management, and two-level logic minimization to compress the set of found assignments. In addition, a cache table is introduced into the satisfy-all procedure. It is a difficult problem for a satisfy-all procedure to detect the case that a previous result can be reused. This paper shows that the case can be detected by comparing sets of undetermined variables and clauses. Experimental results show that the proposed algorithm can check more circuits than binary decision diagram-based and previous SAT-based model-checking algorithms.-
dc.description.sponsorshipThis work was supported in part by the Korea Science and Engineering Foundation through the MICROS Center, in part by the Ministry of Science and Technology and the Ministry of Commerce, Industry and Energy through the System IC 2010 project, and in part by the Ministry of Information and Communication through the IT-SoC project. This paper was recommended by Associate Editor J. H. Kukula.en
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectAUTOMATIC VERIFICATION-
dc.subjectREACHABILITY ANALYSIS-
dc.subjectTEMPORAL LOGIC-
dc.titleSAT-based unbounded symbolic model checking-
dc.typeArticle-
dc.identifier.wosid000226478700001-
dc.identifier.scopusid2-s2.0-13144268611-
dc.type.rimsART-
dc.citation.volume24-
dc.citation.issue2-
dc.citation.beginningpage129-
dc.citation.endingpage140-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS-
dc.identifier.doi10.1109/TCAD.2004.841068-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorPark, In-Cheol-
dc.contributor.nonIdAuthorKang, HJ-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorBoolean satisfiability checking (SAT)-
dc.subject.keywordAuthorformal verification-
dc.subject.keywordAuthorsymbol manipulation-
dc.subject.keywordAuthorsymbolic model checking-
dc.subject.keywordPlusAUTOMATIC VERIFICATION-
dc.subject.keywordPlusREACHABILITY ANALYSIS-
dc.subject.keywordPlusTEMPORAL LOGIC-
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