DC Field | Value | Language |
---|---|---|
dc.contributor.author | Daehyun Chung | ko |
dc.contributor.author | Chunghyun Ryu | ko |
dc.contributor.author | Hyungsoo Kim | ko |
dc.contributor.author | Choonheung Lee | ko |
dc.contributor.author | Jinhan Kim | ko |
dc.contributor.author | Kicheol Bae | ko |
dc.contributor.author | Jiheon Yu | ko |
dc.contributor.author | Hoijun Yoo | ko |
dc.contributor.author | Kim, Joungho | ko |
dc.date.accessioned | 2013-03-06T20:24:36Z | - |
dc.date.available | 2013-03-06T20:24:36Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2006-01 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, no.1, pp.274 - 286 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/88347 | - |
dc.description.abstract | This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SIMULTANEOUS SWITCHING NOISE | - |
dc.subject | GROUND BOUNCE | - |
dc.subject | PLL JITTER | - |
dc.subject | POWER | - |
dc.subject | INTERCONNECT | - |
dc.subject | CIRCUITS | - |
dc.subject | DESIGN | - |
dc.subject | PLANES | - |
dc.title | Chip-package hybrid clock distribution network and DLL for low jitter clock delivery | - |
dc.type | Article | - |
dc.identifier.wosid | 000234305600030 | - |
dc.identifier.scopusid | 2-s2.0-31344476827 | - |
dc.type.rims | ART | - |
dc.citation.volume | 41 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 274 | - |
dc.citation.endingpage | 286 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.contributor.localauthor | Kim, Joungho | - |
dc.contributor.nonIdAuthor | Daehyun Chung | - |
dc.contributor.nonIdAuthor | Chunghyun Ryu | - |
dc.contributor.nonIdAuthor | Hyungsoo Kim | - |
dc.contributor.nonIdAuthor | Choonheung Lee | - |
dc.contributor.nonIdAuthor | Jinhan Kim | - |
dc.contributor.nonIdAuthor | Kicheol Bae | - |
dc.contributor.nonIdAuthor | Jiheon Yu | - |
dc.contributor.nonIdAuthor | Hoijun Yoo | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | chip-package hybrid clock distribution network | - |
dc.subject.keywordAuthor | chip-package hybrid delay-locked loop (DLL) | - |
dc.subject.keywordAuthor | clock distribution | - |
dc.subject.keywordAuthor | low delay clock distribution | - |
dc.subject.keywordAuthor | low jitter clock distribution | - |
dc.subject.keywordAuthor | on-chip repeaters | - |
dc.subject.keywordAuthor | simultaneous switching noise (SSN) | - |
dc.subject.keywordPlus | SIMULTANEOUS SWITCHING NOISE | - |
dc.subject.keywordPlus | GROUND BOUNCE | - |
dc.subject.keywordPlus | PLL JITTER | - |
dc.subject.keywordPlus | POWER | - |
dc.subject.keywordPlus | INTERCONNECT | - |
dc.subject.keywordPlus | CIRCUITS | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | PLANES | - |
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