DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han S.-W. | ko |
dc.contributor.author | Yoon E. | ko |
dc.date.accessioned | 2013-03-06T19:15:48Z | - |
dc.date.available | 2013-03-06T19:15:48Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2006 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.42, no.6, pp.335 - 337 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/88104 | - |
dc.description.abstract | An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2 mu m in a test chip fabricated using 0.18 mu m CMOS process and has demonstrated fixed pattern noise less than 0.46%. | - |
dc.language | English | - |
dc.publisher | INSTITUTION ENGINEERING TECHNOLOGY -IET | - |
dc.subject | ON-A-CHIP | - |
dc.title | Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors | - |
dc.type | Article | - |
dc.identifier.wosid | 000236772400014 | - |
dc.identifier.scopusid | 2-s2.0-33645234847 | - |
dc.type.rims | ART | - |
dc.citation.volume | 42 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 335 | - |
dc.citation.endingpage | 337 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el:20064189 | - |
dc.contributor.localauthor | Han S.-W. | - |
dc.contributor.nonIdAuthor | Yoon E. | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | ON-A-CHIP | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.