DC Field | Value | Language |
---|---|---|
dc.contributor.author | Maji, Debabrata | ko |
dc.contributor.author | Duttagupta, S. P. | ko |
dc.contributor.author | Rao, V. Rarngopal | ko |
dc.contributor.author | Yeo, Chia Ching | ko |
dc.contributor.author | Cho, Byung Jin | ko |
dc.date.accessioned | 2013-03-06T18:47:23Z | - |
dc.date.available | 2013-03-06T18:47:23Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2007-08 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.28, no.8, pp.731 - 733 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/88014 | - |
dc.description.abstract | In this letter, we focus on the border-trap characterization of TaN/HfO2/Si and TaN/HfO2/strained-Si/Si0.8Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 run. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained-Si/Si0.8Ge0.2. These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | MOS DEVICES | - |
dc.subject | GATE STACK | - |
dc.subject | NOISE | - |
dc.subject | NMOSFETS | - |
dc.subject | DIELECTRICS | - |
dc.subject | QUALITY | - |
dc.subject | IMPACT | - |
dc.title | Border-trap characterization in high-kappa strained-si MOSFETs | - |
dc.type | Article | - |
dc.identifier.wosid | 000248315400021 | - |
dc.identifier.scopusid | 2-s2.0-34547751876 | - |
dc.type.rims | ART | - |
dc.citation.volume | 28 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 731 | - |
dc.citation.endingpage | 733 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/LED.2007.902086 | - |
dc.contributor.localauthor | Cho, Byung Jin | - |
dc.contributor.nonIdAuthor | Maji, Debabrata | - |
dc.contributor.nonIdAuthor | Duttagupta, S. P. | - |
dc.contributor.nonIdAuthor | Rao, V. Rarngopal | - |
dc.contributor.nonIdAuthor | Yeo, Chia Ching | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | border traps | - |
dc.subject.keywordAuthor | charge pumping | - |
dc.subject.keywordAuthor | hysteresis | - |
dc.subject.keywordAuthor | interface | - |
dc.subject.keywordAuthor | trapping | - |
dc.subject.keywordAuthor | strained-Si | - |
dc.subject.keywordAuthor | 1/f noise | - |
dc.subject.keywordPlus | MOS DEVICES | - |
dc.subject.keywordPlus | GATE STACK | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | NMOSFETS | - |
dc.subject.keywordPlus | DIELECTRICS | - |
dc.subject.keywordPlus | QUALITY | - |
dc.subject.keywordPlus | IMPACT | - |
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