P-type floating gate for retention and P/E window improvement of flash memory devices

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dc.contributor.authorShen, Chenko
dc.contributor.authorPu, Jingko
dc.contributor.authorLi, Ming-Fuko
dc.contributor.authorCho, Byung Jinko
dc.date.accessioned2013-03-06T12:13:16Z-
dc.date.available2013-03-06T12:13:16Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2007-08-
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.54, no.8, pp.1910 - 1917-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10203/86952-
dc.description.abstractA Flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) V-th window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled Flash memory cells. Both device simulation and experimental verification are presented.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectEEPROMS-
dc.titleP-type floating gate for retention and P/E window improvement of flash memory devices-
dc.typeArticle-
dc.identifier.wosid000248390600013-
dc.identifier.scopusid2-s2.0-34547883096-
dc.type.rimsART-
dc.citation.volume54-
dc.citation.issue8-
dc.citation.beginningpage1910-
dc.citation.endingpage1917-
dc.citation.publicationnameIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.identifier.doi10.1109/TED.2007.900680-
dc.contributor.localauthorCho, Byung Jin-
dc.contributor.nonIdAuthorShen, Chen-
dc.contributor.nonIdAuthorPu, Jing-
dc.contributor.nonIdAuthorLi, Ming-Fu-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorcoupling ratio (CR)-
dc.subject.keywordAuthorelectrically erasable programmable read-only memory (EEPROM)-
dc.subject.keywordAuthorFlash memory-
dc.subject.keywordAuthorfloating gate-
dc.subject.keywordAuthorp-type-
dc.subject.keywordAuthorretention-
dc.subject.keywordPlusEEPROMS-
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