A CMOS power amplifier with an adaptive bias scheme for mobile radio frequency identification reader applications

Abstract

A 900-MHz linear power amplifier with an adaptive bias scheme is fabricated using a 0.25-mu m CMOS technology. The power amplifier operates over the range of 860-960 MHz, which is the ultrahigh-frequency band for radio frequency identification (RFID). All matching networks and RF chokes are implemented on a chip. The developed power amplifier provides a 1-dB-gain-compression point (P-1 (dB)) of 27 dBm and a power-added-efficiency (PAE) of 28% at the P-1 (dB). The adaptive bias scheme enables the power amplifier to reduce the quiescent power consumption from 280 to 80 mW by adjusting the gate voltage of power transistors as a,function of the input power. (c) 2007 Wiley Periodicals, Inc.