A 10-bit 50-MS/s pipelined ADC with opamp cuffent reuse

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dc.contributor.authorRyu, Seung-Takko
dc.contributor.authorSong, BSko
dc.contributor.authorBacrania, Kko
dc.date.accessioned2013-03-06T06:18:52Z-
dc.date.available2013-03-06T06:18:52Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2007-03-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.42, pp.475 - 485-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/86107-
dc.description.abstractPower and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 mu W/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for I- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0 degrees to 85 degrees C and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1.1 x 1.3 mm(2) using a 0.18-mu m complementary metal oxide semiconductor (CMOS) process.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectCMOS ADC-
dc.subjectA/D CONVERTER-
dc.subjectSFDR-
dc.titleA 10-bit 50-MS/s pipelined ADC with opamp cuffent reuse-
dc.typeArticle-
dc.identifier.wosid000245110400002-
dc.identifier.scopusid2-s2.0-33847752977-
dc.type.rimsART-
dc.citation.volume42-
dc.citation.beginningpage475-
dc.citation.endingpage485-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.doi10.1109/JSSC.2006.891718-
dc.contributor.localauthorRyu, Seung-Tak-
dc.contributor.nonIdAuthorSong, BS-
dc.contributor.nonIdAuthorBacrania, K-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorcapacitor-array multiplying digital-to-analog converter (MDAC)-
dc.subject.keywordAuthordigital-to-analog converter (DAC)-
dc.subject.keywordAuthorlow-power technique-
dc.subject.keywordAuthoropamp-sharing-
dc.subject.keywordAuthorpipelined analog-to-digital converter (ADC)-
dc.subject.keywordAuthorswitched-opamp-
dc.subject.keywordPlusCMOS ADC-
dc.subject.keywordPlusA/D CONVERTER-
dc.subject.keywordPlusSFDR-
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