DC Field | Value | Language |
---|---|---|
dc.contributor.author | Huang, XJ | ko |
dc.contributor.author | Lee, WC | ko |
dc.contributor.author | Kuo, C | ko |
dc.contributor.author | Hisamoto, D | ko |
dc.contributor.author | Chang, LL | ko |
dc.contributor.author | Kedzierski, J | ko |
dc.contributor.author | Anderson, E | ko |
dc.contributor.author | Takeuchi, H | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | Asano, K | ko |
dc.contributor.author | Subramanian, V | ko |
dc.contributor.author | King, TJ | ko |
dc.contributor.author | Bokor, J | ko |
dc.contributor.author | Hu, CM | ko |
dc.date.accessioned | 2013-03-05T03:11:58Z | - |
dc.date.available | 2013-03-05T03:11:58Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.48, no.5, pp.880 - 886 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/85220 | - |
dc.description.abstract | High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I-dsat of 820 muA/mum at V-ds = V-gs = 1.2 V and T-ox = 2.5 nm, Devices showed good performance down to a gate-length of 18 nm, Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects, Simulations indicate that the FinFET structure can work down to 10 nm gate length, Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | POLYCRYSTALLINE SIXGE1-X FILMS | - |
dc.subject | MOSFET | - |
dc.title | Sub-50 nm p-channel FinFET | - |
dc.type | Article | - |
dc.identifier.wosid | 000168361000010 | - |
dc.identifier.scopusid | 2-s2.0-0035340554 | - |
dc.type.rims | ART | - |
dc.citation.volume | 48 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 880 | - |
dc.citation.endingpage | 886 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Huang, XJ | - |
dc.contributor.nonIdAuthor | Lee, WC | - |
dc.contributor.nonIdAuthor | Kuo, C | - |
dc.contributor.nonIdAuthor | Hisamoto, D | - |
dc.contributor.nonIdAuthor | Chang, LL | - |
dc.contributor.nonIdAuthor | Kedzierski, J | - |
dc.contributor.nonIdAuthor | Anderson, E | - |
dc.contributor.nonIdAuthor | Takeuchi, H | - |
dc.contributor.nonIdAuthor | Asano, K | - |
dc.contributor.nonIdAuthor | Subramanian, V | - |
dc.contributor.nonIdAuthor | King, TJ | - |
dc.contributor.nonIdAuthor | Bokor, J | - |
dc.contributor.nonIdAuthor | Hu, CM | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | double-gate MOSFETs | - |
dc.subject.keywordAuthor | fully depleted | - |
dc.subject.keywordAuthor | MOS devices | - |
dc.subject.keywordAuthor | scaled CMOS | - |
dc.subject.keywordAuthor | short-channel effect | - |
dc.subject.keywordAuthor | silicon-germanium (SiGe) | - |
dc.subject.keywordAuthor | SOI MOSFETs | - |
dc.subject.keywordPlus | POLYCRYSTALLINE SIXGE1-X FILMS | - |
dc.subject.keywordPlus | MOSFET | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.