Synthesis of application-specific coprocessor for core-based ASIC design

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This paper presents an efficient approach for a hard/software are partitioning problem: synthesis of an application-specific coprocessor which accelerates an embedded software running on a main processor. Given a set of data how graphs (DFGs), most of previous hardware/software partitioning approaches have focused on mapping DFGs to hardware or soft ware. Their common weaknesses are that 1) they ignore various implementation alternatives in realizing DFGs as hardware based on the assumption that: only a single hardware implementation exists for a DFG, and that 2) they dent consider the effect of merging on hardware area when synthesizing a coprocessor by merging DFGs. To deal wish the first issue, we formulate both the mapping of DFGs to hardware or software and the selection of the appropriate hardware implementation for each DFG as a single integer programming problem, and then apply an iterative algorithm based on the Kernighan and Lin's heuristic to solve the problem. To reduce the CPU time, ive have devised data structures that quickly calculate costs of hardware implementations. To deal with the second issue, our method links DFGs with dummy nodes to produce a single large DFG, and then syn thesizes a target coprocessor by globally scheduling the DFG and allocating its datapath. Experimental results demonstrate that our approach outperforms the previous approach based on genetic algorithm (GA) in both the coprocessor area and the CPU time.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2001-02
Language
English
Article Type
Article
Keywords

HARDWARE

Citation

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E84A, no.2, pp.604 - 613

ISSN
0916-8508
URI
http://hdl.handle.net/10203/83905
Appears in Collection
EE-Journal Papers(저널논문)
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