DC Field | Value | Language |
---|---|---|
dc.contributor.author | Eum, NW | ko |
dc.contributor.author | Kim, T | ko |
dc.contributor.author | Kyung, Chong-Min | ko |
dc.date.accessioned | 2013-03-04T19:38:03Z | - |
dc.date.available | 2013-03-04T19:38:03Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2004-07 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTERS, v.53, pp.829 - 842 | - |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | http://hdl.handle.net/10203/83867 | - |
dc.description.abstract | This paper presents a new performance and routability driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). A key contribution of our work is the overcoming of one essential limitation of the previous routing algorithms: inaccurate estimations of routing density that were too general for symmetrical FPGAs. To this end, we formulate an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs and utilize it consistently in global and detailed routings. With an introduction to the proposed accurate routing metrics, we describe a new routing algorithm, called cost-effective net-decomposition-based routing, which is fast and yet produces remarkable routing results in terms of both routability and net/path delays. We performed extensive experiments to show the effectiveness of our algorithm based on the proposed cost metrics. | - |
dc.language | English | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.subject | PERFORMANCE | - |
dc.title | CeRA: A router for symmetrical FPGAs based on exact routing density evaluation | - |
dc.type | Article | - |
dc.identifier.wosid | 000221406600004 | - |
dc.identifier.scopusid | 2-s2.0-3242696273 | - |
dc.type.rims | ART | - |
dc.citation.volume | 53 | - |
dc.citation.beginningpage | 829 | - |
dc.citation.endingpage | 842 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.nonIdAuthor | Eum, NW | - |
dc.contributor.nonIdAuthor | Kim, T | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | FPGAs | - |
dc.subject.keywordAuthor | routing algorithms | - |
dc.subject.keywordAuthor | performance | - |
dc.subject.keywordAuthor | routability | - |
dc.subject.keywordAuthor | routing density | - |
dc.subject.keywordPlus | PERFORMANCE | - |
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