Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis

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dc.contributor.authorKim, BWko
dc.contributor.authorKyung, Chong-Minko
dc.date.accessioned2013-03-04T19:37:43Z-
dc.date.available2013-03-04T19:37:43Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2002-06-
dc.identifier.citationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.10, no.3, pp.240 - 252-
dc.identifier.issn1063-8210-
dc.identifier.urihttp://hdl.handle.net/10203/83865-
dc.description.abstractThis paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IN from different sources and how to integrate the selected IN using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IN with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectEMBEDDED SYSTEMS-
dc.subjectSELECTION-
dc.titleExploiting intellectual properties with imprecise design costs for system-on-chip synthesis-
dc.typeArticle-
dc.identifier.wosid000178926900005-
dc.identifier.scopusid2-s2.0-0036625410-
dc.type.rimsART-
dc.citation.volume10-
dc.citation.issue3-
dc.citation.beginningpage240-
dc.citation.endingpage252-
dc.citation.publicationnameIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.nonIdAuthorKim, BW-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorexploration-
dc.subject.keywordAuthorhierarchical bus architecture-
dc.subject.keywordAuthorimprecise design costs-
dc.subject.keywordAuthorintellectual property (IP)-
dc.subject.keywordAuthorMP3 decoding-
dc.subject.keywordAuthoron-chip bus-
dc.subject.keywordAuthorpossibilistic mixed integer linear programming-
dc.subject.keywordAuthor(PMILP)-
dc.subject.keywordAuthorsystem-on-chip (SoC)-
dc.subject.keywordAuthoruncertainty-
dc.subject.keywordPlusEMBEDDED SYSTEMS-
dc.subject.keywordPlusSELECTION-
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