An energy-efficient data cache with byte-repeat pattern encoding

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The on-chip cache is a significant source of the energy consumption of today's processors. Several data compression techniques including Frequent Value Caches are proposed to reduce the energy consumption in the data cache memories. However, the preceding approach has some problems, such as the monitoring time to find the frequent values dedicated for each program and the additional registers to store the frequent values. By studying the behavior of MiBench and MediaBench programs, we observed that many data values stored in the data cache have a few word patterns in which one byte is repeated and/or the rest of bytes are all zeros. These values can be represented with one byte and the pattern type bits. We propose a new energy-efficient data cache, the Byte-Repeat Pattern Cache, which employs this encoding scheme.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2008-10
Language
English
Article Type
Article
Citation

IEICE ELECTRONICS EXPRESS, v.5, no.19, pp.833 - 839

ISSN
1349-2543
DOI
10.1587/elex.5.833
URI
http://hdl.handle.net/10203/8237
Appears in Collection
CS-Journal Papers(저널논문)
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