64-bit carry-select adder with reduced area
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Y | ko |
| dc.contributor.author | Kim, Lee-Sup | ko |
| dc.date.accessioned | 2013-03-04T08:33:43Z | - |
| dc.date.available | 2013-03-04T08:33:43Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2001-05 | - |
| dc.identifier.citation | ELECTRONICS LETTERS, v.37, no.10, pp.614 - 615 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/82185 | - |
| dc.description.abstract | A carry-select adder can be implemented by using a single ripple-carry adder and an add-one circuit instead of using dual ripple-carry adders. A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty. The proposed 64 bit carry-select adder requires 42% fewer transistors than the conventional carry-select adder. | - |
| dc.language | English | - |
| dc.publisher | IEE-INST ELEC ENG | - |
| dc.title | 64-bit carry-select adder with reduced area | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000168899100005 | - |
| dc.identifier.scopusid | 2-s2.0-0035837218 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 37 | - |
| dc.citation.issue | 10 | - |
| dc.citation.beginningpage | 614 | - |
| dc.citation.endingpage | 615 | - |
| dc.citation.publicationname | ELECTRONICS LETTERS | - |
| dc.contributor.localauthor | Kim, Lee-Sup | - |
| dc.contributor.nonIdAuthor | Kim, Y | - |
| dc.type.journalArticle | Article | - |
- Appears in Collection
- EE-Journal Papers(저널논문)
- Files in This Item
- There are no files associated with this item.
This item is cited by other documents in WoS
| ⊙ Detail Information in WoSⓡ | Click to see |  |
| ⊙ Cited 64 items in WoS | Click to see citing articles in |  |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.