DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lindert, N | ko |
dc.contributor.author | Chang, LL | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | Anderson, EH | ko |
dc.contributor.author | Lee, WC | ko |
dc.contributor.author | King, TJ | ko |
dc.contributor.author | Bokor, J | ko |
dc.contributor.author | Hu, CM | ko |
dc.date.accessioned | 2013-03-04T01:30:14Z | - |
dc.date.available | 2013-03-04T01:30:14Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-10 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.22, no.10, pp.487 - 489 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/81313 | - |
dc.description.abstract | N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. Drive current for typical devices is found to be above 500 muA/mum (or 1mA/mum, depending on the definition of the width of the double-gate device) for V-g - V-t = V-d = 1 V. The electrical gate oxide thickness in these devices is 21A, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Sub-60-nm quasi-planar FinFETs fabricated using a simplified process | - |
dc.type | Article | - |
dc.identifier.wosid | 000171432400011 | - |
dc.identifier.scopusid | 2-s2.0-0035475617 | - |
dc.type.rims | ART | - |
dc.citation.volume | 22 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 487 | - |
dc.citation.endingpage | 489 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/55.954920 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Lindert, N | - |
dc.contributor.nonIdAuthor | Chang, LL | - |
dc.contributor.nonIdAuthor | Anderson, EH | - |
dc.contributor.nonIdAuthor | Lee, WC | - |
dc.contributor.nonIdAuthor | King, TJ | - |
dc.contributor.nonIdAuthor | Bokor, J | - |
dc.contributor.nonIdAuthor | Hu, CM | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | double-gate | - |
dc.subject.keywordAuthor | double-resist process | - |
dc.subject.keywordAuthor | fin | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | MOSFET | - |
dc.subject.keywordAuthor | short-channel effects | - |
dc.subject.keywordAuthor | SiGe gate | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.