DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, CH | ko |
dc.contributor.author | Im, YH | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2013-03-03T22:08:52Z | - |
dc.date.available | 2013-03-03T22:08:52Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2004-05 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.40, pp.597 - 598 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/80659 | - |
dc.description.abstract | An adaptive cache indexing is proposed to reduce the memory bandwidth required for fetching texture image data by reducing the cache miss-rate through adaptive selection of index bits. By designing a texture mapping hardware including a texture cache, the number of cache miss and total cycles are examined for texture mapping from cycle-accurate HDL simulations on some test scenes. The number of cache miss and total cycles were reduced by 23% and 8.9% respectively by the adaptive cache indexing. | - |
dc.language | English | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.title | Miss-rate reduction in texture cache by adaptive cache indexing | - |
dc.type | Article | - |
dc.identifier.wosid | 000221793900018 | - |
dc.identifier.scopusid | 2-s2.0-2942532411 | - |
dc.type.rims | ART | - |
dc.citation.volume | 40 | - |
dc.citation.beginningpage | 597 | - |
dc.citation.endingpage | 598 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el:20040439 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Kim, CH | - |
dc.contributor.nonIdAuthor | Im, YH | - |
dc.type.journalArticle | Article | - |
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