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Efficient shared cache architectures for time-sensitive applications = 시간민감한 응용프로그램을 위한 효율적인 공유 캐쉬 구조link Lee, Myoungjun; Kim, Soontae; et al, 한국과학기술원, 2020 |
MH Cache: A Multi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems![]() Park, Jungwoo; Lee, Myoungjun; Kim, Soontae; Ju, Minho; Hong, Jeongkyu, ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, v.16, no.3, 2019-08 |
Performance Controllable Shared Cache Architecture for Multi-Core Soft Real-Time Systems Lee, Myoungjun; Kim, Soontae, IEEE International Conference on Computer Design, pp.519 - 522, IEEE, 2013-10-07 |
Time-sensitivity-aware shared cache architecture for multi-core embedded systems Lee, Myoungjun; Kim, Soontae, JOURNAL OF SUPERCOMPUTING, v.75, no.10, pp.6746 - 6776, 2019-10 |
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