DC Field | Value | Language |
---|---|---|
dc.contributor.author | Loh, WY | ko |
dc.contributor.author | Cho, Byung Jin | ko |
dc.contributor.author | Joo, MS | ko |
dc.contributor.author | Li, MF | ko |
dc.contributor.author | Chan, DSH | ko |
dc.contributor.author | Mathew, S | ko |
dc.contributor.author | Kwong, DL | ko |
dc.date.accessioned | 2013-03-03T13:47:09Z | - |
dc.date.available | 2013-03-03T13:47:09Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2004-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, v.4, no.4, pp.696 - 703 | - |
dc.identifier.issn | 1530-4388 | - |
dc.identifier.uri | http://hdl.handle.net/10203/78936 | - |
dc.description.abstract | Charge trapping and breakdown.:mechanism in p- and n-channel MOSFETs with an HfA1(x)O(y) and TaN metal electrode are investigated. Using carrier separation measurement technique, it is possible to clearly distinguish two different breakdown mechanisms: a high-K bulk initiated and an interfacial layer initiated breakdown. A model of charge trapping at different spatial locations in HfAlx O-y with a TaN gate structure is proposed to explain the polarity dependence of charge trapping characteristics and breakdown mechanisms. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Charge trapping and breakdown mechanism in HfAIO/TaN gate stack analyzed using carrier separation | - |
dc.type | Article | - |
dc.identifier.wosid | 000226617100017 | - |
dc.identifier.scopusid | 2-s2.0-13444309342 | - |
dc.type.rims | ART | - |
dc.citation.volume | 4 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 696 | - |
dc.citation.endingpage | 703 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | - |
dc.identifier.doi | 10.1109/TDMR.2004.838416 | - |
dc.contributor.localauthor | Cho, Byung Jin | - |
dc.contributor.nonIdAuthor | Loh, WY | - |
dc.contributor.nonIdAuthor | Joo, MS | - |
dc.contributor.nonIdAuthor | Li, MF | - |
dc.contributor.nonIdAuthor | Chan, DSH | - |
dc.contributor.nonIdAuthor | Mathew, S | - |
dc.contributor.nonIdAuthor | Kwong, DL | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | gate leakage current | - |
dc.subject.keywordAuthor | gate stacks | - |
dc.subject.keywordAuthor | high-K dielectrics | - |
dc.subject.keywordAuthor | reliability | - |
dc.subject.keywordAuthor | tunneling | - |
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