Early analysis tools for system-on-a-chip design

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dc.contributor.authorDarringer, JAko
dc.contributor.authorBergamaschi, RAko
dc.contributor.authorBhattacharya, Sko
dc.contributor.authorBrand, Dko
dc.contributor.authorHerkersdorf, Ako
dc.contributor.authorMorrell, JKko
dc.contributor.authorNair, IIko
dc.contributor.authorSagmeister, Pko
dc.contributor.authorShin, Youngsooko
dc.date.accessioned2013-03-03T12:05:04Z-
dc.date.available2013-03-03T12:05:04Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2002-11-
dc.identifier.citationIBM JOURNAL OF RESEARCH AND DEVELOPMENT, v.46, no.6, pp.691 - 707-
dc.identifier.issn0018-8646-
dc.identifier.urihttp://hdl.handle.net/10203/78594-
dc.description.abstractThe paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic(R) Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design.-
dc.languageEnglish-
dc.publisherIBM CORP-
dc.titleEarly analysis tools for system-on-a-chip design-
dc.typeArticle-
dc.identifier.wosid000179130100005-
dc.identifier.scopusid2-s2.0-0012182852-
dc.type.rimsART-
dc.citation.volume46-
dc.citation.issue6-
dc.citation.beginningpage691-
dc.citation.endingpage707-
dc.citation.publicationnameIBM JOURNAL OF RESEARCH AND DEVELOPMENT-
dc.contributor.localauthorShin, Youngsoo-
dc.contributor.nonIdAuthorDarringer, JA-
dc.contributor.nonIdAuthorBergamaschi, RA-
dc.contributor.nonIdAuthorBhattacharya, S-
dc.contributor.nonIdAuthorBrand, D-
dc.contributor.nonIdAuthorHerkersdorf, A-
dc.contributor.nonIdAuthorMorrell, JK-
dc.contributor.nonIdAuthorNair, II-
dc.contributor.nonIdAuthorSagmeister, P-
dc.type.journalArticleArticle-
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