A dual burn-in policy for defect-tolerant memory products using the number of repairs as a quality indicator

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dc.contributor.authorTong, SHko
dc.contributor.authorYum, Bong-Jinko
dc.date.accessioned2008-10-28T06:33:56Z-
dc.date.available2008-10-28T06:33:56Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2008-03-
dc.identifier.citationMICROELECTRONICS RELIABILITY, v.48, pp.471 - 480-
dc.identifier.issn0026-2714-
dc.identifier.urihttp://hdl.handle.net/10203/7689-
dc.description.abstractIn most existing studies on the optimization of burn-in for semiconductor products, all chips are treated equally and subjected to burn-in of the same duration (i.e. a single burn-in (SBI) policy is employed). However, the quality levels of chips before burn-in are not the same in general, and therefore, it may be more advantageous to treat chips differently at the burn-in process based on appropriate quality indicators. This paper considers defect-tolerant memory products and develops a dual burn-in (DBI) policy in which the chips submitted to burn-in are classified into two groups according to the number of repairs, a quality indicator that can be obtained from the wafer probe test results, and different burn-in durations are applied to different groups of chips. Then, cost models are developed for the SBI and DBI policies, and their relative performances are compared in terms of the expected total cost per chip. The effectiveness of the proposed DBI policy is demonstrated using the actual data for a certain type of 256M DRAM products. (C) 2007 Elsevier Ltd. All rights reserved.-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD-
dc.subjectPOLYNOMIAL REGRESSION-MODELS-
dc.subjectPROPORTIONAL HAZARDS MODELS-
dc.subjectRELIABILITY-
dc.subjectYIELD-
dc.subjectTIME-
dc.subjectCOST-
dc.subjectVLSI-
dc.titleA dual burn-in policy for defect-tolerant memory products using the number of repairs as a quality indicator-
dc.typeArticle-
dc.identifier.wosid000254692400018-
dc.identifier.scopusid2-s2.0-39449095743-
dc.type.rimsART-
dc.citation.volume48-
dc.citation.beginningpage471-
dc.citation.endingpage480-
dc.citation.publicationnameMICROELECTRONICS RELIABILITY-
dc.identifier.doi10.1016/j.microrel.2007.03.009-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorYum, Bong-Jin-
dc.contributor.nonIdAuthorTong, SH-
dc.type.journalArticleArticle-
dc.subject.keywordPlusPOLYNOMIAL REGRESSION-MODELS-
dc.subject.keywordPlusPROPORTIONAL HAZARDS MODELS-
dc.subject.keywordPlusRELIABILITY-
dc.subject.keywordPlusYIELD-
dc.subject.keywordPlusTIME-
dc.subject.keywordPlusCOST-
dc.subject.keywordPlusVLSI-
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