High breakdown voltage P-HEMT using single gate lithography and two-step gate recess process

Abstract

In this paper, we report a two-step gate recess process that uses the single step gate patterning and the sequentially selective dry and wet etchings to improve the breakdown voltage of low noise P-HEMT device. The current-voltage (I-V) and gate-to-drain reverse diode characteristics of P-HEMT fabricated by using two-step gate recess are compared with those by using the conventional single gate recess. The high gate-to-drain breakdown voltage (-11.7 V), low output conductance (19 mS/mm), and low leakage current (0.4 mu A) in pinch-off region of I-V characteristics are obtained for the low noise P-HEMT fabricated with two-step gate recess process.