A new single-clock flip-flop for half-swing clocking

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A new hip-hop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. V-cc is supplied to the random logic circuits and flip-flops while V-cc/2 is supplied to the clock network and some parts of the Aip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
1999-11
Language
English
Article Type
Article
Keywords

CMOS; LOGIC

Citation

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E82A, no.11, pp.2521 - 2526

ISSN
0916-8508
URI
http://hdl.handle.net/10203/75882
Appears in Collection
EE-Journal Papers(저널논문)
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