Fast precise interrupt handling without associative searching in multiple out-of-order issue processors

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This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
1999-03
Language
English
Article Type
Article
Keywords

FUNCTIONAL UNIT; PERFORMANCE

Citation

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E82D, no.3, pp.645 - 653

ISSN
0916-8532
URI
http://hdl.handle.net/10203/75807
Appears in Collection
EE-Journal Papers(저널논문)
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