3-D packages including package stack, module stack, and bare die stack have become important in packaging technology because of their very compact size and excellent electrical performance. Among the three 3-D packages, bare die stacking is seen to be a state-of-art 3-D packaging technology in terms of package efficiency and electrical performance. A new design of 3-D bare die stack package has been established and the process optimization has been conducted. According to the newly developed design, the prototype of the newly designed 3-D bare die stack package has been successfully demonstrated. There have been several remarkable improvements in this new 3-D package design compared with the other conventional 3-D bare die stack packages. The unique features of this package design are the sidewall insulation prior to the I/O redistribution, which produces (1) better chip-to-wafer yield and (2) significant process simplification in the following fabrication steps. And the fabricated prototype 3-D stacked packages successfully meet the preliminary reliability tests.