High speed latchup resistant CMOS data output buffer for submicrometre DRAM application

Abstract

A latchup resistant CMOS data output buffer for 0.5 mu m CMOS DRAM is designed, fabricated and measured. It has a floating n-well which adjusts its voltage level to suppress the leakage current. Its leakage current is controlled to be < 10nA with the bonding pad voltage ranging from 0 to 10V. The propagation delay is measured to be shorter by 3.8ns than that of an NMOS data output buffer.