Design of high efficiency interleaved active clamp zero voltage switching forward converter

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A high efficiency interleaved active clamp forward converter with self-driven synchronous rectifiers for a modular power processor is presented. To simplify the gate drive circuits, the n-p MOSFETs coupled active clamp method is used. An efficiency of about 90% for a load range of 50-100% is achieved. Details of design for the power stage and current mode control circuit are provided, and also some experimental results are given.
Publisher
TAYLOR FRANCIS LTD
Issue Date
1999-07
Language
English
Article Type
Article
Keywords

SYNCHRONOUS RECTIFICATION

Citation

INTERNATIONAL JOURNAL OF ELECTRONICS, v.86, no.7, pp.875 - 889

ISSN
0020-7217
DOI
10.1080/002072199133094
URI
http://hdl.handle.net/10203/74936
Appears in Collection
EE-Journal Papers(저널논문)
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