Path-classified trace cache for improving hit ratio in wide-issue processors

Abstract

In this gaper, an instruction-cache scheme called Multi-Path Tracing is proposed to enhance the trace cache. Paths are classified to improve the trace cache hit ratio bg reducing the path conflict and basic blocks are joined to reduce the hardware cast, needed to implement the trace cache. Simulation results for various SPEC integer benchmarks show that the proposed scheme increases the hit ratio by more than. 25% and the effective fetch size by 10%.