DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | King, TJ | ko |
dc.contributor.author | Hu, CM | ko |
dc.date.accessioned | 2007-06-27T06:25:56Z | - |
dc.date.available | 2007-06-27T06:25:56Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2002-01 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.23, no.1, pp.25 - 27 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/688 | - |
dc.description.abstract | A spacer lithography process technology, which uses a sacrificial layer and spacer layer formed by chemical vapor deposition (CVD), has been developed. It has been applied to make a sub-40-nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this spacer lithography technology yields better critical dimension uniformity than conventional optical or e-beam lithography and defines smaller features beyond the limit of current lithography technology. It also provides a doubling of feature density for a given lithography pitch, which increases current by a factor of two. To demonstrate this spacer lithography technology, Si-fin structures have been patterned for planar double-gate CMOS FinFET devices. | - |
dc.description.sponsorship | The authors would like to thank the University of California- Berkeley Microlab staffs for their support in device fabrication. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Nanoscale CMOS spacer FinFET for the terabit era | - |
dc.type | Article | - |
dc.identifier.wosid | 000173259800009 | - |
dc.identifier.scopusid | 2-s2.0-0036163060 | - |
dc.type.rims | ART | - |
dc.citation.volume | 23 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 25 | - |
dc.citation.endingpage | 27 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | King, TJ | - |
dc.contributor.nonIdAuthor | Hu, CM | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | chemical mechanical polishing (CMP) | - |
dc.subject.keywordAuthor | critical dimension (CD) | - |
dc.subject.keywordAuthor | double-gate | - |
dc.subject.keywordAuthor | finFET | - |
dc.subject.keywordAuthor | gate planarization | - |
dc.subject.keywordAuthor | nanoscale CMOS | - |
dc.subject.keywordAuthor | silicon-on-insulator (SOI) | - |
dc.subject.keywordAuthor | spacer etch | - |
dc.subject.keywordAuthor | spacer lithography | - |
dc.subject.keywordAuthor | thin-body | - |
dc.subject.keywordAuthor | uniformity | - |
dc.subject.keywordPlus | MOSFET | - |
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