DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, LL | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | Ha, DW | ko |
dc.contributor.author | Ranade, P | ko |
dc.contributor.author | Xiong, SY | ko |
dc.contributor.author | Bokor, J | ko |
dc.contributor.author | Hu, CM | ko |
dc.contributor.author | King, TJ | ko |
dc.date.accessioned | 2007-06-27T06:15:57Z | - |
dc.date.available | 2007-06-27T06:15:57Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2003-11 | - |
dc.identifier.citation | PROCEEDINGS OF THE IEEE, v.91, no.11, pp.1860 - 1873 | - |
dc.identifier.issn | 0018-9219 | - |
dc.identifier.uri | http://hdl.handle.net/10203/687 | - |
dc.description.abstract | Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations. | - |
dc.description.sponsorship | This work was supported by the Semiconductor Research Corporation under Contract 2000-NJ-850 and the Microelectronics Advanced Research Corporation under Contract 2001-MT-887. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | WORK FUNCTION | - |
dc.subject | INVERSION-LAYERS | - |
dc.subject | NANOSCALE CMOS | - |
dc.subject | SI MOSFETS | - |
dc.subject | GATE | - |
dc.subject | TECHNOLOGY | - |
dc.subject | METAL | - |
dc.subject | MOBILITY | - |
dc.subject | TRANSISTOR | - |
dc.subject | FINFET | - |
dc.title | Extremely scaled silicon nano-CMOS devices | - |
dc.type | Article | - |
dc.identifier.wosid | 000186025200009 | - |
dc.identifier.scopusid | 2-s2.0-5744251698 | - |
dc.type.rims | ART | - |
dc.citation.volume | 91 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 1860 | - |
dc.citation.endingpage | 1873 | - |
dc.citation.publicationname | PROCEEDINGS OF THE IEEE | - |
dc.identifier.doi | 10.1109/JPROC.2003.818336 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Chang, LL | - |
dc.contributor.nonIdAuthor | Ha, DW | - |
dc.contributor.nonIdAuthor | Ranade, P | - |
dc.contributor.nonIdAuthor | Xiong, SY | - |
dc.contributor.nonIdAuthor | Bokor, J | - |
dc.contributor.nonIdAuthor | Hu, CM | - |
dc.contributor.nonIdAuthor | King, TJ | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | metal gate | - |
dc.subject.keywordAuthor | molybdenum | - |
dc.subject.keywordAuthor | MOSFET | - |
dc.subject.keywordAuthor | nanotechnology | - |
dc.subject.keywordAuthor | scaling | - |
dc.subject.keywordAuthor | ultrathin body (UTB) | - |
dc.subject.keywordPlus | WORK FUNCTION | - |
dc.subject.keywordPlus | INVERSION-LAYERS | - |
dc.subject.keywordPlus | NANOSCALE CMOS | - |
dc.subject.keywordPlus | SI MOSFETS | - |
dc.subject.keywordPlus | GATE | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | METAL | - |
dc.subject.keywordPlus | MOBILITY | - |
dc.subject.keywordPlus | TRANSISTOR | - |
dc.subject.keywordPlus | FINFET | - |
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