DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ha, D | ko |
dc.contributor.author | Takeuchi, H | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | King, TJ | ko |
dc.date.accessioned | 2007-06-27T06:07:39Z | - |
dc.date.available | 2007-06-27T06:07:39Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2004-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.51, no.12, pp.1989 - 1996 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/685 | - |
dc.description.abstract | Damage-free sputter deposition and highly selective dry-etch processes have been developed for molybdenum (Mo) metal gate technology, for application to fully depleted silicon-on-insulator ( devices such as the ultrathin body (UTB) MOSFET and double-gate FinFET. A plasma charge trap effectively eliminates high-energy particle bombardment during Mo sputtering; hence the gate-dielectric integrity (TDDB, Q(BD)) is significantly improved and the field-effect mobility in Mo-gated MOSFETs follows the universal mobility curve. The effects of etch process parameters such as chlorine (Cl-2) and oxygen (O-2) gas flow rate, and source and bias radio frequence powers, were investigated in order to optimize the Mo etch rate and selectivity to SiO2. A highly selective etch process was successfully applied to pattern Mo gate electrodes for UTB MOSFETs and FinFETs without leaving any residue or stringers. Measured electrical characteristics and physical analysis results are discussed. | - |
dc.description.sponsorship | This work was supported in part by the MARCO Focus Center on Materials, Structures, and Devices, funded by the Massachusetts Institute of Technology, in part by MARCO under Contract 2001-MT-887, and in part by DARPA under Grant MDA972-01-1-0035. The review of this paper was arranged by Editor C.-Y. Lu. D. Ha, H. Takeuchi, and T.-J. King are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail: eawon@eecs.berkeley.edu). Y.-K. Choi is with the Department of Electrical Engineering and Computer Sciences,Korea Advanced Institute of Science and Technology, Daejeon,Korea. Digital Object Identifier 0.1109/TED.2004.839752 | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SI MOSFETS | - |
dc.subject | METAL | - |
dc.subject | DEPOSITION | - |
dc.subject | NITRIDE | - |
dc.title | Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs | - |
dc.type | Article | - |
dc.identifier.wosid | 000225362900005 | - |
dc.identifier.scopusid | 2-s2.0-10644265317 | - |
dc.type.rims | ART | - |
dc.citation.volume | 51 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 1989 | - |
dc.citation.endingpage | 1996 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2004.839752 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Ha, D | - |
dc.contributor.nonIdAuthor | Takeuchi, H | - |
dc.contributor.nonIdAuthor | King, TJ | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | complementary metal-oxide-semiconductor | - |
dc.subject.keywordAuthor | (CMOS) | - |
dc.subject.keywordAuthor | dry etching | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | fully depleted silicon-on-insulator (FD SOI) | - |
dc.subject.keywordAuthor | molybdenum metal gate | - |
dc.subject.keywordAuthor | sputter | - |
dc.subject.keywordAuthor | ultrathin body | - |
dc.subject.keywordPlus | SI MOSFETS | - |
dc.subject.keywordPlus | METAL | - |
dc.subject.keywordPlus | DEPOSITION | - |
dc.subject.keywordPlus | NITRIDE | - |
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